Power uptime and Power-to-X efficiency are driving SOC Demand
Solid Oxide Cell stacks are scaling through two operating modes. SOFC generates firm on-site power. SOEC produces hydrogen and e-fuels efficiently from steam. As deployments of stacks grow from pilots to gigawatts, manufacturers focus on interface stability and repeatable manufacturing to protect lifetime performance.
SOFC (Solid Oxide Fuel Cell)
Distributed on-site power where uptime and fast deployment matter, including data centers and microgrids.
SOEC (Solid Oxide Electrolysis Cell)
Industrial hydrogen and e-fuels where efficiency and long-life stacks define project economics.
Reduce what slows your Solid Oxide Cell production
Architectures differ across manufacturers. The scale up blockers are consistent.
They show up as ASR drift, chromium risk, and manufacturing variability.
Across Solid Oxide Cell (SOC) production, the recurring constraints are:
Interconnect degradation
Oxidation, chromium volatilization, and rising ASR drift
Production variability
Non uniform thickness or porosity, edge effects, and yield loss
Interface reactions and diffusion
Insulating phases and instability at electrode electrolyte interfaces
Forming and thermal cycling damage
Cracks or delamination when coatings are not process designed
When these appear, the outcome is predictable.
Lifetime drops, yield drops, qualification slows, and production ramps get delayed.
Where we apply PVD to strengthen SOC stack reliability
These are the layers that most often decide ASR stability, degradation rate, and manufacturing yield. Pick the area you are working on and we can scope an evaluation plan around your geometry and operating window.
Interconnect protective and contact layers
Interconnect coatings that stabilize ASR and reduce chromium-driven degradation through forming and thermal cycling.
Electrolyte
barrier layers
Barrier layers that limit inter-diffusion and interface reactions to improve durability and broaden material compatibility.
Functional
electrolytes
Functional electrolyte films engineered for dense, uniform, gas-tight layers that deliver consistent stack performance.
Make thin film performance repeatable with PVD process control
Physical Vapor Deposition (PVD) gives you tighter control over thin-film thickness, density and composition, so performance is more repeatable as you scale.
Thickness control
Stabilize ASR trends over life with tighter film thickness and composition control
Dense microstructure
Reduce pinholes and improve high-temperature interface stability
Uniform coverage
Coat complex geometries consistently to reduce edge effects and variability
Low-stress deposition
Protect parts through forming and thermal cycling with stable process windows
Scale repeatability
Maintain repeatable output from trials to pilot and volume ramps
Qualify against your geometry and operating window
Start with our current Solid Oxide Cell (SOC) PVD coating capability, then extend it with joint trials to match your architecture, dimensions, and validation needs.
Component | Interconnect Coating | Electrolyte Barrier Layers | Functional Electrolytes |
|---|---|---|---|
Coating Material | Spinel
(customizable) | Ceramic (GDC/YSZ)
(customizable) | Ceramic (GDC/YSZ)
(customizable) |
Substrate Material | Stainless Steel / Alloys | Ceramic / Metal
supported Ceramic | Ceramic / Metal
supported Ceramic |
Substrate Size* | up to 20cm x 30 cm | up to 20cm x 30 cm | up to 20cm x 30 cm |
Coating Thickness* | ≤ 60µm | ≤ 3µm | ≤ 15µm |
Key Functional Benefits | Minimize Cr-volatilization
Low ASR at 600–800 °C | Prevent formation of insulating reaction layers
Improve cathode/electrolyte interface stability | Dense ionic-conducting films
Compatible with next-gen SOFC/SOEC architectures |
Note: *Supported structures include flat plates, discs, small tubular forms. Additional geometries, alloys, dimensions, and layer stacks can be evaluated through joint trials.
Choose how you scale up
Some OEM teams want a fast evaluation route.
Others want to bring deposition in house for tighter control during production ramp. Sydrogen supports both.
Coating service
Rapid trials on your substrates and parts with metrology and process documentation to support internal validation
Inline PVD equipment
An equipment led route for OEMs who want automated, high throughput deposition and tighter control of production ramp yield
Frequently Asked Questions (FAQ)
What is ASR and why does it matter in SOFC and SOEC?
ASR stands for area-specific resistance. It is a measure of the electrical resistance contributed by interfaces in the stack, typically reported per unit area. In SOFC and SOEC, ASR matters because it directly impacts efficiency, heat generation, and long-term performance stability. As stacks age, interconnect oxidation and interface changes can cause ASR to drift upward, reducing output (SOFC) or increasing power required for hydrogen production (SOEC).
How does PVD help reduce chromium-related degradation risk?
Many SOC stacks use ferritic stainless steel interconnects, where chromium species can migrate or volatilize at high temperature and contribute to degradation mechanisms at interfaces. PVD helps by depositing thin, dense, uniform films that act as a controlled protective or functional layer on the interconnect surface. Because PVD allows tighter control of film composition, thickness, and microstructure, it can improve layer consistency across production geometries and reduce variability that often accelerates chromium-related failure modes.
What is the difference between interconnect coating, barrier layer, and functional electrolyte?
They address different parts of the stack and different failure modes: •Interconnect coating (protective/contact layer): targets the metallic interconnect to maintain stable electrical contact and reduce high-temperature degradation mechanisms over time. •Barrier layer: sits at critical interfaces to limit inter-diffusion and undesirable reactions that can form insulating phases and destabilize performance. •Functional electrolyte: is a dense ionic-conducting layer intended to support uniformity and gas tightness, helping deliver consistent stack performance.
Can PVD coat formed or corrugated interconnects?
Yes, depending on geometry and fixturing. PVD is well-suited to many real-world parts, including formed features, but coating uniformity on corrugations and deep features depends on factors such as line-of-sight constraints, part orientation, tooling/fixturing design, and process settings. The typical path is to start with coupons or representative formed samples, review coverage results, then tune the process window for the production geometry.
What data do you provide in evaluation runs?
Evaluation runs are designed to support OEM qualification decisions. A typical data pack may include: •Coating thickness (and uniformity mapping where applicable) •Adhesion checks (method aligned to sample type and program needs) •Microstructure indicators (e.g., SEM-based observations and elemental mapping where applicable)
What information should I share to start an evaluation?
Minimum: target layer (interconnect/barrier/electrolyte), substrate alloy/material, part dimensions, operating temperature window, and the failure mode you want to address (ASR drift, Cr risk, cycling damage, etc.).
How do I choose between coating service and inline equipment?
A common approach is service first to confirm performance and qualification fit, then consider inline equipment once the deposition window and throughput targets are clear for volume ramp.